1. Field of the Invention
This invention relates to a semiconductor integrated circuit device such as memory, photoelectric converting device, signal processing device, etc. to be mounted on various electronic instruments, particularly to an insulated gate type transistor thereof.
2. Related Background Art
In recent years, as an effort for higher integration, it has been desired to apply practically finely worked functional devices such as development of MOS transistor with the gate length of submicron order, etc.
FIG. 1 to FIG.3 are schematic cross-sectional views showing the structure of the MOS transistor of the prior art. FIG. 1 is N-MOS transistor with a single drain structure having a gate 201, an oxidized film 202, a source 203 and a drain 204, which is the simplest structure, and its production process is also simple. However, with the progress of finer formation of the device, when the gate length becomes 1.2 .mu.m or less, deterioration of the actuation of the MOS transistor will occur. FIG. 2 has the low concentration regions 205 and 206 provided for relaxing the electrical field between the source and the drain for preventing it, and is called the LDD (lightly doped drain) structured. Further, as the LSI for DRAM which is most progressed in finer formation, a thin Transistor cell (TTC) as shown in FIG. 3 has been proposed. TTC has a groove provided in the semiconductor substrate 211, and a transistor and a capacitor are formed at the same time. More specifically, it has a gate oxidized film 213, with the channel portion 214 being located on the side face of the gate oxidized film. In the groove at the lower part of the gate 212, a polycrystalline Si 215 is filled and deposited to form an electrode of the capacitor for memory, with its surface being oxidized to form an inductor film 216 for capacitor. The buried source 217 is formed at the upper part of the polycrystalline Si 216. Further, it is equipped with the word line 218 with the polycrystalline Si, the n+ diffusion layer as the drain and pit line, and is separated electrically through the separation oxidized film 220 from the adjacent cells. On the insulation film 221, the interlayer insulation film 222 are respectively formed the wiring patterns 223 and 224. The TTC, having the MOS transistor and capacitor formed in the vertical direction, has such advantages that it is smaller in area, and also erroneous actuation due to influence of .alpha.-ray will occur with difficulty, and further it is free from parasitic transistor. Region 219 has a relatively low concentration of impurities and is provided for relaxing the electrical field between the source and drain regions.
However, the groove type transistor cell as described above has still room to be improved in the following points.
1) In the semiconductor device shown in FIG. 3, only with respect to the transistor portion, the aspect ratio (groove depth/opening diameter) is about 2, and therefore the yield is lowered by the defect which occurs by Si etching, and further uniform formation of the insulation film of good quality can be formed with difficulty in the groove, thus posing a problem in reliability.
2) Further, polycrystalline silicon which is the control electrode member to be generally used in TTC cannot make the resistivity about 1 m.OMEGA.cm or lower even if an impurity may be diffused to the maximum extent, whereby it is impossible to make smaller the propagation, delay time which determine the speed of the transistor. Even if a silicide (Si metal alloy) may be employed in place of polycrystalline silicon, the resistivity is about 100 to 200 .mu..OMEGA.cm and no transistor of high speed, high yield and high reliability could be obtained.
3) Further, generally speaking, the control electrode is deposited on the semiconductor device surface uniformly and therefore the surface of the control electrode reflects the uneveness itself of the groove, as opposite to flattening. Shortly speaking, for maintaining of high reliability of the wiring deposited on the control electrode, an insulation film must be attached on the control electrode, and flattening effected according to the method of etch-back. This method is a method which leaves the resist only at the concavity thickly and cuts simultaneously the insulation film at the resist concavity in rf plasma, and since the influence of rf exerted on MOS transistor is extremely great, the risk of impairing the yield, reliability has been very great.